This invention relates generally to power-up reset circuits and more particularly, it relates to an improved CMOS power-on reset circuit which includes hysteresis switching means for turning off a reset signal when a first predetermined trip level has been reached and for turning on the reset signal when a second predetermined trip level has been reached and which is lower than the first predetermined trip level.
In a variety of CMOS or bipolar digital integrated circuit devices, such as flip-flops, latches, counters, memory state registers and the like, the outputs thereof can have two or more stable states. It is often desirable to initialize or reset these types of logic and/or memory circuits to a particular known logic state prior to their normal operation every time when power is first applied (i.e., "power-up"). As is generally well-known, this initialization process is commonly achieved by a reset signal generated by a power-on reset circuit which is applied for a brief period of time when the power supply voltage is ramping up so as to reset or initialize the outputs of the digital integrated circuit devices. Accordingly, this proper initialization ensures the operating state of the various logic and/or memory circuits in the digital integrated circuit devices as well as simplifies test procedures to be performed on them. This reset signal is then switched off after the power supply voltage exceeds a predetermined level, which is below the normal power supply voltage.
However, in the event of a transient noise occurring after the power supply voltage has exceeded the predetermined level but while it is still ramping up, this will cause the disadvantage of generating an unwanted reset signal which tends to interfere with the normal operation of the digital integrated circuit devices.
It is generally desirable to prevent the generation of the reset signal due to this transient noise in order that the digital integrated circuit devices are maintained in the functional state and to permit the generation of the reset signal only in the event of an actual power-down. Accordingly, it would be desirable to provide an improved power-on reset circuit which avoids the generation of a reset signal due to transient noise after the power supply voltage has exceeded the predetermined level. Further, in order to reduce the amount of space required, it would be expedient to have the power-on reset circuit formed as a part of the same monolithic semiconductor integrated circuit chip containing the digital logic devices.